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DATA SHEET
MOS INTEGRATED CIRCUIT
PD705102
V832TM 32-BIT MICROPROCESSOR
DESCRIPTION
The PD705102 (V832) is a 32-bit RISC microprocessor for embedded control applications, with a highperformance 32-bit V830TM processor core and many peripheral functions such as a SDRAM/ROM controller, 4channel DMA controller, real-time pulse unit, serial interface, interrupt controller, and power management. In addition to high interrupt response speed and optimized pipeline structure, the V832 offers sum-of-products operation instructions, concatenated shift instructions, and high-speed branch instructions to realize multimedia functions, and therefore can provide high performance in multimedia systems such as Internet/intra-net systems, car navigation systems, digital still cameras, and color faxes. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. V832 User's Manual -- Hardware: U13577E V830 FamilyTM User's Manual -- Architecture: U12496E
FEATURES
* CPU function * V830-compatible instructions * Instruction cache: * Instruction RAM: * Data cache: * Data RAM: * Minimum number of instruction execution cycles: * Number of general purpose registers: 32 bits x 32 * Memory space and I/O space: 4 Gbytes each * Interrupt/exception processing function * Non-maskable: External input: 1 * Maskable: External input: 8 (of which 4 are multiplexed with internal sources) Internal source: 11 types * Bus control function * Wait control function * Memory access control function
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U13675EJ2V1DS00 (2nd edition) Date Published July 1999 N CP(K) Printed in Japan
* DMA controller: 4 channels * Serial interface function 4 Kbytes 4 Kbytes 4 Kbytes 4 Kbytes 1 cycle * Asynchronous serial interface (UART): 1 channel * Clocked serial interface (CSI): * Timer/counter function * 16-bit timer/event counter: 1 channel * 16-bit interval timer: * Port function: 21 I/O ports * Clock generation function: PLL clock synthesizer (6x or 8x multiplication) * Standby function: HALT, STOP, and power management modes * Debug function * Debug-dedicated synchronous serial interface: * Trace-dedicated interface: 1 channel 1 channel 1 channel 1 channel * Dedicated baud rate generator (BRG): 1 channel
The mark
shows major revised points.
(c)
1999
PD705102
ORDERING INFORMATION
Part Number Package 160-pin plastic LQFP (fine pitch) (24 x 24 mm) 160-pin plastic LQFP (fine pitch) (24 x 24 mm)
PD705102GM-143-8ED PD705102GM-133-8ED
PIN CONFIGURATION (TOP VIEW)
* 160-pin plastic LQFP (fine pitch) (24 x 24 mm)
PD705102GM-143-8ED PD705102GM-133-8ED
VDD_O D31 D30 D29 D28 D27 D26 D25 D24 GND_I VDD_I GND_O VDD_O D23 D22 D21 D20 D19 D18 D17 D16 GND_O VDD_O D15 D14 D13 D12 D11 D10 D9 D8 GND_O VDD_O D7 D6 D5 D4 D3 D2 GND_I 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
GND_O CS1 CS0 WE RAS UUDQM ULDQM LUDQM LLDQM VDD_O GND_O SDCLKOUT CKE CAS A1 A2 A3 A4 VDD_I GND_I VDD_O GND_O A5 A6 A7 A8 A9 A10 A11 VDD_O GND_O A12 A13 A14 A15 A16 A17 A18 A19 VDD_O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
VDD_I D1 D0 GND_O VDD_O MRD MWR LLBEN LUBEN ULBEN UUBEN IOWR IORD BCYST READY R/W HLDRQ HLDAK GND_O VDD_O CS2 CS3 CS4 CS5 CS6 CS7 TC/STOPAK PORTA1/DMAAK0 PORTA3/DMAAK1 PORTA5/DMAAK2 PORTA7/DMAAK3 PORTA0/DMARQ0 PORTA2/DMARQ1 PORTA4/DMARQ2 PORTA6/DMARQ3 PORTB7/INTP03 PORTB6/INTP02 PORTB4/INTP01 PORTB2/INTP00 GND_I
Caution
Directly connect the IC1 (Internally connected 1) pin to GND_O.
2
GND_O A20 A21 A22 A23 CLKOUT TRCDATA0 TRCDATA1 TRCDATA2 TRCDATA3 DDI DCK DMS DDO VDD_PLL X1 X2 GND_PLL VDD_I GND_I IC1 BT16B RESET NMI DRST CMODE PORT3/RXD PORT4/TXD PORT2/SI PORT1/SO PORT0/SCLK VDD_O GND_O INTP10/TO10 INTP12/TO11 PORTB5/INTP11 PORTB3/INTP13 PORTB0/TI PORTB1/TCLR VDD_I
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Data Sheet U13675EJ2V1DS00
PD705102
PIN NAMES
A1 to A23: BCYST: BT16B: CAS: CKE: CLKOUT: CMODE: CS0 to CS7: D0 to D31: DCK: DDI: DDO: Address Bus Bus Cycle Start Boot Bus Size 16-bit Column Address Strobe Clock Enable Clock Out Clock Mode Chip Select Data Bus Debug Clock Debug Data Input Debug Data Output DMA Acknowledge DMARQ0 to DMARQ3: DMA Request DMS: DRST: GND_I: GND_O: GND_PLL: HLDAK: HLDRQ: IC1: Debug Mode Select Debug Reset Ground Ground PLL Ground Hold Acknowledge Hold Request Internally Connected Interrupt Request From Peripheral IORD: IOWR: LLBEN: LLDQM: LUBEN: LUDQM: MRD: MWR: I/O Read I/O Write Lower Lower Byte Enable Lower Lower DQ Mask enable Lower Upper Byte Enable Lower Upper DQ Mask enable Memory Read Memory Write NMI: PORT0 to PORT4, PORTA0 to PORTA7, PORTB0 to PORTB7: Port R/W: RAS: READY: RESET: RXD: SCLK: SDCLKOUT: SI: SO: STOPAK: TC: TCLR: TI: TO10, TO11: TXD: ULBEN: ULDQM: UUBEN: UUDQM: VDD_I: VDD_O: VDD_PLL: WE: X1, X2: Bus Read or Write Status Row Address Strobe Ready Reset Receive Data Serial Clock SDRAM Clock Out Serial Input Serial Output Stop Acknowledge Terminal Count Timer Clear Timer Input Timer Output Transmit Data Upper Lower Byte Enable Upper Lower DQ Mask enable Upper Upper Byte Enable Upper Upper DQ Mask enable Power Supply (2.5 V) Power Supply (3.3 V) PLL Power Supply (2.5 V) Write Enable Crystal Oscillator Non-Maskable Interrupt Request
DMAAK0 to DMAAK3:
TRCDATA0 to TRCDATA3: Trace Data
INTP00 to INTP03, INTP10 to INTP13:
Data Sheet U13675EJ2V1DS00
3
PD705102
INTERNAL BLOCK DIAGRAM
DCK DMS DDI DDO TRCDATA3 to TRCDATA0 DRST X1 X2 CLKOUT SDCLKOUT RESET NMI TI, TCLR INTP10/TO10, INTP12/TO11 INTP11, INTP13 INTP00 to INTP03
DCU
CG BCU SYU V830 core
RPU
ICU
R/W IOWR IORD MWR MRD UUBEN, ULBEN, LUBEN, LLBEN READY BT16B BCYST CS7 to CS0 A23 to A1 D31 to D0 HLDRQ HLDAK RAS CAS UUDQM, ULDQM, LUDQM, LLDQM CKE WE STOPAK CMODE
PIO
SCLK SO SI TXD RXD
BRG CSI UART DMAC
TC DMARQ3 to DMARQ0 DMAAK3 to DMAAK0
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Data Sheet U13675EJ2V1DS00
PD705102
CONTENTS 1. PIN FUNCTIONS .................................................................................................................................. 6
1.1 1.2 Port Pins ....................................................................................................................................................... 6 Non-Port Pins ............................................................................................................................................... 7
2. 3. 4. 5. 6. 7.
INTERNAL UNITS ................................................................................................................................ 9 CPU FUNCTION ................................................................................................................................. 11 INTERRUPT/EXCEPTION PROCESSING FUNCTION ..................................................................... 12 BUS CONTROL FUNCTION .............................................................................................................. 14 WAIT CONTROL FUNCTION ............................................................................................................. 14 MEMORY ACCESS CONTROL FUNCTION ...................................................................................... 15
7.1 7.2 SDRAM Control Function .......................................................................................................................... 15 Page-ROM Control Function ..................................................................................................................... 17
8. 9.
DMA FUNCTION ................................................................................................................................ 18 SERIAL INTERFACE FUNCTION ...................................................................................................... 20
9.1 9.2 9.3 Asynchronous Serial Interface (UART) .................................................................................................... 20 Clocked Serial Interface (CSI) ................................................................................................................... 22 Baud Rate Generator (BRG) ...................................................................................................................... 23
10. TIMER/COUNTER FUNCTION .......................................................................................................... 24 11. PORT FUNCTION .............................................................................................................................. 27 12. CLOCK GENERATION FUNCTION ................................................................................................... 32 13. STANDBY FUNCTION ....................................................................................................................... 33 14. RESET/NMI CONTROL FUNCTION .................................................................................................. 35 15. INSTRUCTIONS ................................................................................................................................. 36
15.1 Instruction Format ..................................................................................................................................... 36 15.2 Instructions (Listed Alphabetically) ......................................................................................................... 38
16. ELECTRICAL SPECIFICATIONS ...................................................................................................... 48 17. PACKAGE DRAWING ........................................................................................................................ 75 18. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 76
Data Sheet U13675EJ2V1DS00
5
PD705102
1. PIN FUNCTIONS
1.1 Port Pins
Pin Name PORT0 PORT1 PORT2 PORT3 PORT4 PORTA0 PORTA1 PORTA2 PORTA3 PORTA4 PORTA5 PORTA6 PORTA7 PORTB0 PORTB1 PORTB2 PORTB3 PORTB4 PORTB5 PORTB6 PORTB7 I/O PORTB 8-bit input/output port. Input/output can be specified in 1-bit units. I/O I/O PORTA 8-bit input/output port. Input/output can be specified in 1-bit units. I/O Schmitt I/O I/O Schmitt I/O Function PORT 5-bit input/output port. Input/output can be specified in 1-bit units. Alternate Function SCLK SO SI RXD TXD DMARQ0 DMAAK0 DMARQ1 DMAAK1 DMARQ2 DMAAK2 DMARQ3 DMAAK3 TI TCLR INTP00 INTP13 INTP01 INTP11 INTP02 INTP03
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Data Sheet U13675EJ2V1DS00
PD705102
1.2 Non-Port Pins (1/2)
Pin Name D0 to D31 A1 to A23 READY HLDRQ HLDAK MRD UUBEN ULBEN LUBEN LLBEN IORD IOWR MWR BT16B BCYST R/W RESET X1 X2 CLKOUT CMODE CS2, CS7 CS3 to CS6 STOPAK INTP10 INTP11 INTP12 INTP13 INTP00 INTP01 INTP02 INTP03 NMI RAS UUDQM ULDQM LUDQM LLDQM 3-state output Non-maskable interrupt SDRAM RAS strobe DQ mask enable (most significant byte: D31 to D24) DQ mask enable (second byte: D23 to D16) DQ mask enable (third byte: D15 to D8) DQ mask enable (least significant byte: D7 to D0) Output Input Input -- Schmitt input Output Input 3-state output Input 3-state output I/O 3-state I/O 3-state output Input Input Output 3-state output Data bus Address bus End of bus cycle enable Bus hold request Bus hold enable Memory read strobe Byte enable output (most significant byte: D31 to D24) Byte enable output (enables second byte: D23 to D16) Byte enable output (enables third byte: D15 to D8) Byte enable output (enables least significant byte: D7 to D0) I/O read strobe I/O write strobe Memory write strobe CS7 space bus size setting Bus cycle start output R/W output Reset input Crystal resonator connection (open when external clock input) Crystal resonator connection/external clock input Bus clock output PLL multiplication factor setting (x6, x8) Memory chip select output Memory I/O chip select output STOP mode report output Maskable interrupts TC TO10 PORTB5 TO11 PORTB3 PORTB2 PORTB4 PORTB6 PORTB7 -- -- -- -- -- -- Function Alternate Function -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Data Sheet U13675EJ2V1DS00
7
PD705102
(2/2)
Pin Name WE CAS CS0 CS1 CKE SDCLKOUT DMARQ0 DMARQ1 DMARQ2 DMARQ3 DMAAK0 DMAAK1 DMAAK2 DMAAK3 TC TO10 TO11 TCLR TI RXD TXD SCLK SI SO DCK DDI DDO DMS DRST TRCDATA0 to TRCDATA3 VDD_I VDD_O GND_I GND_O VDD_PLL GND_PLL Output -- Schmitt input Output Schmitt I/O Schmitt input Output Schmitt input Input Output Input Input Timer 1 clear, start input Timer 1 count clock input UART data input UART data output CSI clock I/O CSI data input CSI data output Debug clock input Debug data input Debug data output Debug mode select DCU reset input Trace data output Positive power supply (2.5 V) Positive power supply (3.3 V) Ground (2.5 V) Ground (3.3 V) PLL (internal clock generator) positive power supply (2.5 V) PLL (internal clock generator) ground potential (2.5 V) DMA transfer end output Timer 1 output Output DMA enable (CH0 to CH3) Output Input I/O 3-state output SDRAM write strobe SDRAM CAS strobe SDRAM chip select SDRAM/SRAM (ROM) chip select SDRAM clock enable SDRAM clock output DMA requests (CH0 to CH3) Function Alternate Function -- -- -- -- -- -- PORTA1 PORTA3 PORTA5 PORTA7 PORTA0 PORTA2 PORTA4 PORTA6 STOPAK INTP10 INTP12 PORTB1 PORTB0 PORT3 PORT4 PORT0 PORT2 PORT1 -- -- -- -- -- -- -- -- -- -- -- --
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Data Sheet U13675EJ2V1DS00
PD705102
2. INTERNAL UNITS
(1) Bus control unit (BCU) Controls the address bus, data bus, and control bus pins. The major functions of BCU are as follows: (a) Bus arbitration Arbitrates the bus mastership among bus masters (CPU, SDRAMC, DMAC, and external bus masters). The bus mastership can be changed after completion of the bus cycle under execution, and in an idle state. (b) Wait control Controls eight areas in the 16-Mbyte space corresponding to eight chip select signals (CS0 through CS7). Generates chip select signals, controls wait states, and selects the type of bus cycle. (c) SDRAM controller Generates commands and controls access to SDRAM. CAS latency is 2 only. (d) ROM controller Accessing ROM with page access function is supported. The bus cycle immediately before and addresses are compared, and wait states are controlled in the normal access (off-page) or page access (on-page) modes. A page width of 8 bytes to 16 bytes can be supported. (2) Interrupt controller (ICU) Services maskable interrupt requests (INTP00 through INTP03, and INTP10 through INTP13) from internal peripheral hardware and external sources. The priorities of these interrupt requests can be specified in units of four groups, and edge-triggered or level-triggered interrupts can be nested. (3) DMA controller (DMAC) Transfers data between memory and I/O in place of CPU. The transfer type is 2-cycle transfer. Two transfer modes, single transfer and demand transfer, are available. (4) Serial interface (UART/CSI/BRG) One asynchronous serial interface (UART) channel and one clocked serial interface (CSI) channel is provided. As the serial clock source, the output of the baud rate generator (BRG) and the bus clock can be selected. (5) Real-time pulse unit (RPU) Provides timer/counter functions. The on-chip 16-bit timer/event counter and 16-bit interval timer can be used to calculate pulse intervals and frequencies, and to output programmable pulses. (6) Clock generator (CG) A frequency six or eight times higher than that of the resonator connected to the X1 and X2 pins is supplied as the operating clock of the CPU. In addition, both a bus clock, which functions as the operating clock of the peripheral units, and SDCLKOUT, which functions as an operating clock, are supplied from the CLKOUT pin. An external clock can be also input instead of connecting a resonator. For reducing the power consumption, the function switching the frequencies of the CPU clock and bus clock with power management control (PMC) is provided.
Data Sheet U13675EJ2V1DS00
9
PD705102
(7) Port (PIO) Provides port functions. Twenty-one I/O ports are available. The pins of these ports can be used as port pins or other function pins. (8) System control unit (SYU) A circuit that eliminates noise on the RESET signal (input)/NMI signal (input) is provided. (9) Debug control unit (DCU) A circuit to realize mapping and trace functions is provided to implement basic debugging functions.
10
Data Sheet U13675EJ2V1DS00
PD705102
3. CPU FUNCTION
The features of the CPU function are as follows: * High-performance 32-bit architecture for embedded control applications * Cache memory Instruction cache: 4 Kbytes Data cache: * Internal RAM Instruction RAM: 4 Kbytes Data RAM: 4 Kbytes * 1-clock pitch pipeline structure * 16-/32-bit length instruction format * Address/data separated type bus * 4-Gbyte linear address * Thirty-two 32-bit general registers * Register/flag hazard interlock is handled by hardware * 16 levels of interrupt response * 16-bit bus fixed function * 16-bit bus system can be constructed * Ideal instructions for any application field: * Sum-of-products operation * Saturation operation * Branch prediction * Concatenation shift * Block transfer instruction 4 Kbytes
Data Sheet U13675EJ2V1DS00
11
PD705102
4. INTERRUPT/EXCEPTION PROCESSING FUNCTION
The features of the interrupt/exception processing function are as follows: * Interrupt * Non-maskable interrupt: 1 source * Maskable interrupt: 15 sources * Priority of the programmable interrupt can be specified in four levels * Nesting interrupt can be controlled according to the priority * Mask can be specified for each maskable interrupt request * Valid edge of an external interrupt request can be specified * Noise elimination circuit provided for the non-maskable interrupt pin (NMI) * Exception * Software exception: 32 sources * Exception trap: 4 sources
The interrupt/exception sources are shown in Tables 4-1 and 4-2. Table 4-1. Reset/Non-maskable Interrupt/Exception Source List
Type Classification Source of Interrupt/Exception NameNote 1 Reset Non-maskable Software exception Interrupt Interrupt Exception RESET NMI TRAP 1nH TRAP 0nH Exception trap Exception NMI FAULT I-OPC DIV0 Cause Reset input NMI input TRAP instruction TRAP instruction Dual exception Fatal exception Illegal instruction code Zero division Exception Code (ECR) FFF0H FFD0H FFBnH FFAnH Note 4 Not affected FF90H FF80H Handler Address FFFFFFF0H Restore PCNote 2 Undefined
FFFFFFD0H next PCNote 3 FFFFFFB0H FFFFFFA0H FFFFFFD0H current PC FFFFFFE0H FFFFFF90H FFFFFF80H next PC
Notes 1. Handler names used in development tools or software. 2. The PC value saved to EIPC/FEPC/DPC when interrupt/exception processing is started. 3. Execution of all instructions cannot be stopped by an interrupt. 4. The exception code of an exception causing a dual exception. Remark n = 0H to FH
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Data Sheet U13675EJ2V1DS00
PD705102
Table 4-2. Maskable Interrupt List
Type Classifi- Group In-Group cation Priority Mask- Interrupt GR3 able 3 2 1 0 GR2 3 2 1 0 GR1 3 2 1 0 GR0 3 2 1 0 Interrupt Source Name Cause Unit -- RPU UART
Exception Code
Handler AddressNote 3
Restore
Note 1 HCCW.IHA=0 HCCW.IHA=1 PC
RESERVED Reserved INTOV1 INTSER INTP03 INTSR INTST INTCSI INTP02 INTDMA INTP10/ INTCC10 INTP11/ INTCC11 INTP01 INTCM4 INTP12/ INTCC12 INTP13/ INTCC13 INTP00 Timer 1 overflow UART receive error INTP03 pin input UART receive end UART transmit end
FEF0H FFFFFEF0H FE0000F0H next Note 2 FEE0H FFFFFEE0H FE0000E0H PC FED0H FFFFFED0H FE0000D0H
External FEC0H FFFFFEC0H FE0000C0H UART UART FEB0H FFFFFEB0H FE0000B0H FEA0H FFFFFEA0H FE0000A0H FE90H FFFFFE90H FE000090H FFFFFE80H FE000080H FFFFFE70H FE000070H FFFFFE60H FE000060H FFFFFE50H FE000050H FFFFFE40H FE000040H FFFFFE30H FE000030H FFFFFE20H FE000020H FFFFFE10H FE000010H FFFFFE00H FE000000H
CSI transmit/receive end CSI INTP02 pin input DMA transfer end INTP10 pin input/ coincidence of CC10 INTP11 pin input/ coincidence of CC11 INTP01 pin input Coincidence of CM4 INTP12 pin input/ coincidence of CC12 INTP13 pin input/ coincidence of CC13 INTP00 pin input
External FE80H DMAC FE70H
External/ FE60H RPU External/ FE50H RPU External FE40H RPU FE30H
External/ FE20H RPU External/ FE10H RPU External FE00H
Notes 1. The PC value saved to EIPC when interrupt processing is started. 2. Execution of all instructions cannot be stopped by an interrupt. 3. FFFFFEn0H can be selected as a handler address when HCCW.IHA = 0, and FE0000n0H can be selected when HCCW.IHA = 1 (n = 0H to FH). Caution The exception codes and handler addresses of the maskable interrupts shown above are the values if the default priority (IGP = E4H) is used. The correspondence between the interrupt source and the handler address is changed from Table 4-2 if the priority of the group (GR0 to GR3) is changed according to the value of the interrupt group priority register (IGP).
Data Sheet U13675EJ2V1DS00
13
PD705102
5. BUS CONTROL FUNCTION
The features of the bus control function are as follows: * SDRAM, Page-ROM, SRAM (ROM) or I/O can be directly connected * SDRAM read/write access with 1 bus clock minimum * SDRAM byte access control with four xxDQM signals * Wait control with READY signal * RAM, ROM or I/O byte access control with four xxBEN signals * 32-/16-bit bus width can be set every CS space * When the 16-bit memory or I/O are accessed by data bus, the external data bus width can be set by the data bus width control register (DBC). Remarks 1. xxBEN: LLBEN, LUBEN, ULBEN, UUBEN 2. xxDQM: LLDQM, LUDQM, ULDQM, UUDQM
6. WAIT CONTROL FUNCTION
The features of the wait control function are as follows: * Controls 8 blocks in accordance with I/O and memory spaces * Linear address space of each block: 16 Mbytes * Bus cycle select function Block 0: Block 1: Block 2: Block 7: SDRAM SDRAM, SRAM (ROM) selectable SRAM (ROM) Page-ROM or SRAM (ROM) selectable
Blocks 3 through 6: I/O or SRAM (ROM) selectable * Data bus width select function Data bus width selectable between 32 bits and 16 bits for each block * Wait control function Blocks 0 and 1: Blocks 5 and 6: SDRAM wait control function is not provided 0 to 15 wait states Blocks 1 through 4 and 7: 0 to 7 wait states * Idle state insertion function 0 to 7 states for each block (bus clock)
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Data Sheet U13675EJ2V1DS00
PD705102
7. MEMORY ACCESS CONTROL FUNCTION
The features of the memory access control function are as follows: * SDRAM control function * Generates RAS, CAS, WE, CKE, LLDQM, LUDQM, ULDQM, and UUDQM signals * Address multiplex: 8 or 9 bits * Timing control of SDRAM access Command interval from REF to REF/ACT: 3 to 6 bus clocks selectable Command interval from ACT to PRE: 3 or 4 bus clocks selectable Command interval from PRE to ACT: 1 or 2 bus clocks selectable Command interval from ACT to READ/WRITE: 1 or 2 bus clocks selectable CAS latency: 2 bus clocks fixed * Auto refresh and self-refresh functions * 8-bank control (4 banks x 2 blocks) * Page-ROM control function * Page size: 8 or 16 bytes * Wait control during page access: 0 to 7 wait states 7.1 SDRAM Control Function The BCU generates RAS, CAS, WE, CS0, CS1, CKE, LLDQM, LUDQM, ULDQM, and UUDQM signals and controls access to the SDRAM. Addresses are output to the SDRAM from the address pins by multiplexing row and column addresses. The connected SDRAM must be of x8 bits or more. The refresh mode is a CAS-before-RAS (CBR) mode, and the refresh cycle can be arbitrarily set. Self refresh is performed in the STOP mode. (1) Address multiplex function An address is multiplexed as shown in Tables 7-1 and 7-2 when row and column addresses are output in the SDRAM cycle, depending on the values of the RAW and CAW bits of the SDRAM configuration register (SDC). In the tables, a1 through a23 indicate the address output by the CPU, and A1 through A15 indicate the address pins of the V832.
Data Sheet U13675EJ2V1DS00
15
PD705102
Table 7-1. Output of Row Address and Column Address (32-bit data width)
External Address Pin BAW 0 RAW 00 CAW 00 Output Timing Column address Row address 0 00 01 Column address Row address 1 00 00 Column address Row address 1 00 01 Column address Row address 1 01 00 Column address Row address A15 (a15) a23 (a15) (a15) (a15) a23 (a15) (a15) a23* a23* A14 (a14) a22 (a14) a23 a22* a22* a23* a23* a22* a22* A13 a21* a21* a22* a22* a21* a21* a22* a22* (a13) a21 A12 AP a20 AP a21 AP a20 AP a21 AP a20 A11 (a11) a19 (a11) a20 (a11) a19 (a11) a20 (a11) a19 A10 (a10) a18 a10 a19 (a10) a18 a10 a19 (a10) a18 A9 to A2 a9 to a2 a17 to a10 a9 to a2 a18 to a11 a9 to a2 a17 to a10 a9 to a2 a18 to a11 a9 to a2 a17 to a10
Remarks 1. * indicates bank address specification. 2. AP is a bit used to specify a command and is fixed to low level. 3. Addresses in parentheses (axx) and A1 and A16 through A23 pins do not multiplex addresses and always output the original values. Table 7-2. Output of Row Address and Column Address (16-bit data width)
External Address Pin BAW 0 RAW 00 CAW 00 Output Timing Column address Row address 0 00 01 Column address Row address 1 00 00 Column address Row address 1 00 01 Column address Row address 1 01 00 Column address Row address A15 (a15) a23 (a15) (a15) (a15) a23 (a15) (a15) (a15) a23 A14 (a14) a22 (a14) a23 (a14) a22 (a14) a23 a22* a22* A13 (a13) a21 (a13) a22 a21* a21* a22* a22* a21* a21* A12 a20* a20* a21* a21* a20* a20* a21* a21* (a12) a20 A11 AP a19 AP a20 AP a19 AP a20 AP a19 A10 (a10) a18 (a10) a19 (a10) a18 (a10) a19 (a10) a18 A9 (a9) a17 a9 a18 (a9) a17 a9 a18 (a9) a17 A8 to A1 a8 to a1 a16 to a9 a8 to a1 a17 to a10 a8 to a1 a16 to a9 a8 to a1 a17 to a10 a8 to a1 a16 to a9
Remarks 1. * indicates bank address specification. 2. AP is a bit used to specify a command and is fixed to low level. 3. Addresses in parentheses (axx) and A16 through A23 pins do not multiplex addresses and always output the original values.
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Data Sheet U13675EJ2V1DS00
PD705102
(2) On-page/off-page decision When the PAE bit of the SDRAM configuration register (SDC) is 1 (page access enabled), whether the SDRAM access to be started is in the same page as the previous SDRAM access is decided. When the PAE bit is 0, the off-page cycle is always started. Table 7-3 shows the relation between an address to be compared and address shift. Table 7-3. Address Compared by on-page/off-page Decision
Address Shift Data Bus Width 16 bits 8 9 a23 to a9 a23 to a10 32 bits a23 to a10 a23 to a11
(3) Refresh function The BCU can automatically generate the distributed auto refresh cycle necessary for refreshing the SDRAM. Whether refreshing is enabled or disabled and the refresh interval are set by the refresh control register (RFC). The BCU has a refresh request queue that can store refresh requests up to seven times. 7.2 Page-ROM Control Function The BCU controls page access to the Page-ROM. Page access to the Page-ROM is valid during burst access. The page size (8 bytes/16 bytes) and the number of wait states (0 wait/1 wait) during page access can be set by using the Page-ROM configuration register (PRC).
Data Sheet U13675EJ2V1DS00
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PD705102
8. DMA FUNCTION
The features of the DMA function are as follows: * Four independent DMA channels * Transfer unit: bytes, half words (2 bytes), words (4 bytes) * Maximum number of transfers: 16,777,216 (224) times * Transfer type: 2-cycle transfer * Two transfer modes * Single transfer mode * Demand transfer mode * Transfer request * External DMARQ pin (x4) * Request from internal peripheral hardware (serial interface (x3 channels) and timer) * Request from software * Transfer source and destination * Between memory and I/O * Between memory and memory * Programmable wait function * DMA transfer end signal output (TC)
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Data Sheet U13675EJ2V1DS00
PD705102
The configuration of the DMA controller (DMAC) is shown below. Figure 8-1. Block Diagram of DMAC
DMAC
Internal I/O
Bus interface
ROM
Internal peripheral I/O bus
BCU DMA source address register (DSA)
External bus
RAM
Address control block
DMA destination address register (DDA)
I/O
Counter control block
DMA transfer count register (DBC)
I/O
Channel control block
DMA control register (DCHC, DC)
DMARQ0 to 3
DMAAK0 to 3
INTDMA
INTCM4
INTCSI
INTSR
INTST
TC
Data Sheet U13675EJ2V1DS00
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PD705102
9. SERIAL INTERFACE FUNCTION
The following channels are provided for the serial interface function. * Asynchronous serial interface (UART): 1 channel * Clocked serial interface (CSI): * Baud rate generator (BRG): 1 channel 1 channel
9.1 Asynchronous Serial Interface (UART) The features of the asynchronous serial interface (UART) are as follows: * Full duplex communication. Receive buffer (RXB) is provided (transmit buffer (TXB) is not provided). * Two-pin configuration (The UART of the V832 does not have the SCLK and CTS pins.) * TXD: Transmit data output pin * RXD: Receive data input pin * Transfer rate: 300 bps to 153600 bps (bus clock: 47.6 MHz, with BRG) : 150 bps to 76800 bps (bus clock: 35.7 MHz, with BRG) * Baud rate generator Serial clock source can be selected from baud rate generator output or bus clock () * Receive error detection function * Parity error * Framing error * Overrun error * Three interrupt sources * Receive error interrupt (INTSER) The interrupt request is generated by ORing three types of receive errors. * Receive end interrupt (INTSR) The receive end interrupt request is generated after completion of receive data transfer from the shift register to the receive buffer in the reception enabled status. * Transmit end interrupt (INTST) The transmit end interrupt request is generated after completion of serial transfer of transmit data (9, 8, or 7 bits) from the shift register. The character length of the transmit/receive data is specified by the ASIM00 and ASIM01 registers. * Character length: 7 or 8 bits : 9 bits (with extension bit appended) * Parity function: Odd, even, 0, or none * Transmit stop bit: 1 or 2 bits
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Data Sheet U13675EJ2V1DS00
PD705102
The configuration of the asynchronous serial interface (UART) is shown below. Figure 9-1. Block Diagram of UART
Internal peripheral I/O bus
16/8
8
RXB0 Receive buffer RXB0L
8
16/8
Mode register
ASIM00 ASIM01
RXD
Receive shift register
Status register ASIS0 Transmit shift register TXS0 TXS0L
TXD
Receive control parity check
INTSER Transmit control parity append INTST INTSR 1/16
1/16
1/2 SEL Baud rate generator
Remark = bus clock : 48 M to 1.3 MHz: @input clock 6x : 36 M to 0.73 MHz: @input clock 8x
Data Sheet U13675EJ2V1DS00
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PD705102
9.2 Clocked Serial Interface (CSI) The features of the clocked serial interface (CSI) are as follows: * High-speed transfer: 12.0 Mbps Max. (bus clock: 48.0 MHz) * Half duplex communication for transmission/reception (buffer is not provided) * Character length: 8 bits * External or internal serial clock selectable The configuration of the clocked serial interface (CSI) is shown below. Figure 9-2. Block Diagram of CSI
Internal peripheral I/O bus
8 8
CSIM0
Mode register SIO0
SO latch Shift register D Q
SI
SO
SCLK
Serial clock control circuit
SEL
1/2
Baud rate generator SEL 1/2, 1/4, 1/8, 1/16, 1/32 prescaler
Serial clock counter
Interrupt control circuit
INTCSI
Remark = bus clock : 48 M to 1.3 MHz: @input clock 6x : 36 M to 0.73 MHz: @input clock 8x
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Data Sheet U13675EJ2V1DS00
PD705102
9.3 Baud Rate Generator (BRG) The features of the baud rate generator (BRG) are as follows: * The serial clock can be used as the baud rate generator output or the divided value of (bus clock) can be used as a baud rate. * The serial clock source is specified by the following registers. * In the case of UART: Specified by the SCLS0 bit of the ASIM00 register. * In the case of CSI: Specified by the CLS02 through CLS00 bits of the CSIM0 register. * The baud rate generator is shared by the UART and CSI. The configuration of the baud rate generator (BRG) is shown below. Figure 9-3. Block Configuration of Baud Rate Generator (BRG)
Internal peripheral I/O bus
BRG0
Compare register
BRCE0
BPR00 to 02
BPRM0
Serial interface (UART/CSI)
TMBRG0
Internal timer
Prescaler
1/2
Remark = bus clock : 48 M to 1.3 MHz: @input clock 6x : 36 M to 0.73 MHz: @input clock 8x
Data Sheet U13675EJ2V1DS00
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PD705102
10. TIMER/COUNTER FUNCTION
The features of the timer/counter function are as follows: * Measures pulse interval and frequency and outputs programmable pulse * 16-bit measurement * Can generate pulses of various shapes (interval pulse, one-shot pulse) * Timer 1 * 16-bit timer/event counter * Source of count clock: * Count clear pin: * Interrupt source: * External pulse output: * Timer 4 * 16-bit interval timer * Count clock selected by dividing system clock * Compare register: x 1 * Interrupt source: 1 type 2 types (selected by dividing system clock, external pulse input) TCLR 5 types 2 pins * Capture/compare register: x 4
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Data Sheet U13675EJ2V1DS00
PD705102
The configurations of timer 1 and timer 4 are shown below. Figure 10-1. Block Configuration of Timer 1
TCLR1
Edge detection Clear & start
/2 /4
m m m/4 m/16
Note 1
TM1 (16 bits) TI
Note 2
INTOV1
Edge detection INTCC10 INTCC11
INTP10 INTP11 INTP12 INTP13
Edge detection Edge detection Edge detection Edge detection
CC10 CC11 CC12 CC13
S R S R
Note 3 Note 3
Q TO10 Q Q TO11 Q INTCC12 INTCC13
Notes 1. Internal count clock 2. When the external count clock is TI: 6.0 MHz or lower: @input clock 6x : 4.5 MHz or lower: @input clock 8x 3. Reset priority Remarks 1. = bus clock: 48 M to 1.3 MHz: @input clock 6x : 36 M to 0.73 MHz: @input clock 8x 2. m = intermediate clock
Data Sheet U13675EJ2V1DS00
25
PD705102
Figure 10-2. Block Configuration of Timer 4
/2 /8
m m/16 m/32
Note
TM4 (16 bits)
Clear & start
CM4
INTCM4
Note Internal count clock Remarks 1. = bus clock: 48 M to 1.3 MHz: @input clock 6x : 36 M to 0.73 MHz: @input clock 8x 2. m = intermediate clock
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Data Sheet U13675EJ2V1DS00
PD705102
11. PORT FUNCTION
The port function features are listed in Table 11-1. Table 11-1. Port Functions
Port PORT0 PORT1 PORT2 PORT3 PORT4 PORTA0 PORTA1 PORTA2 PORTA3 PORTA4 PORTA5 PORTA6 PORTA7 PORTB0 PORTB1 PORTB2 PORTB3 PORTB4 PORTB5 PORTB6 PORTB7 SCLK SO SI RXD TXD DMARQ0 DMAAK0 DMARQ1 DMAAK1 DMARQ2 DMAAK2 DMARQ3 DMAAK3 TI TCLR INTP00 INTP13 INTP01 INTP11 INTP02 INTP03 PORTB 8-bit input/output port. Input/output can be specified in 1-bit units. PORTA 8-bit input/output port. Input/output can be specified in 1-bit units. Control Mode PORT 5-bit input/output port. Input/output can be specified in 1-bit units. Remark
Port configurations are shown in Figures 11-1 to 11-6.
Data Sheet U13675EJ2V1DS00
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PD705102
Figure 11-1. Block Diagram of PORT0
Alternate function pin I/O control Mode register PM
Control mode register PC
Internal peripheral I/O bus
Selector
Selector
SCLK Port register PORT
PORT0
Port read enable SCLK
Figure 11-2. Block Diagram of PORT1 and PORT4
Selector
Alternate function pin I/O control Mode register PM
Control mode register PC
Internal peripheral I/O bus
Selector
Selector
SO (PORT1), TXD (PORT4) Port register PORT
PORT1, PORT4
Port read enable
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Data Sheet U13675EJ2V1DS00
Selector
PD705102
Figure 11-3. Block Diagram of PORT2 and PORT3
Control mode register PC
Mode register PM Internal peripheral I/O bus
Port register PORT
PORT3, PORT2
Port read enable RXD (PORT3), SI (PORT2)
Figure 11-4. Block Diagram of PORTAn (n = 0, 2, 4, or 6)
Control mode register PAC
Mode register PAM
Internal peripheral I/O bus
Selector
Port register PORTA
PORTA6, PORTA4, PORTA2, PORTA0
Selector
Port read enable DMARQ3 to DMARQ0
Data Sheet U13675EJ2V1DS00
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PD705102
Figure 11-5. Block Diagram of PORTAn (n = 1, 3, 5, or 7)
Aiternate function pin I/O control Mode register PAM
Control mode register PAC
Internal peripheral I/O bus
Selector
Port register PORTA
Selector
DMAAK3 to DMAAK0
PORTA7, PORTA5, PORTA3, PORTA1
Port read enable
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Data Sheet U13675EJ2V1DS00
Selector
PD705102
Figure 11-6. Block Diagram of PORTB0 through PORTB7
Control mode register PBC
Mode register PBM Internal peripheral I/O bus
Port register PORTB
PORTB7 to PORTB0
Port read enable Note
Note INTP03 (PORTB7), INTP02 (PORTB6), INTP11 (PORTB5), INTP01 (PORTB4), INTP13 (PORTB3), INTP00 (PORTB2), TCLR (PORTB1), TI (PORTB0) Remark ( ) indicates the corresponding port.
Selector
Data Sheet U13675EJ2V1DS00
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PD705102
12. CLOCK GENERATION FUNCTION
The clock generator generates and controls the CPU clock and bus clock that are supplied to the internal hardware units. PMC and frequencies in PLL/direct modes are shown in Table 12-1 and Table 12-2. Table 12-1. PMC and Frequency in PLL/Direct Modes Example (PD705102-143)
PLL Mode Input clock 23.8 MHz (6 times) PMC x1 x1/2 x1/4 17.85 MHz (8 times) x1 x1/2 x1/4 CPU 142.8 MHz 71.4 MHz 35.7 MHz 142.8 MHz 71.4 MHz 35.7 MHz Bus clock 47.6 MHz 23.8 MHz 11.9 MHz 35.7 MHz 17.85 MHz 8.925 MHz CPU 11.9 MHz 5.95 MHz -- 8.925 MHz 4.463 MHz -- Direct Mode Bus clock 3.96 MHz 1.98 MHz -- 2.231 MHz 1.116 MHz --
Table 12-2. PMC and Frequency in PLL/Direct Modes Example (PD705102-133)
PLL Mode Input clock 22.2 MHz (6 times) PMC x1 x1/2 x1/4 16.7 MHz (8 times) x1 x1/2 x1/4 CPU 133.3 MHz 66.7 MHz 33.3 MHz 133.3 MHz 66.7 MHz 33.3 MHz Bus clock 44.4 MHz 22.2 MHz 11.1 MHz 33.3 MHz 16.7 MHz 8.33 MHz CPU 11.1 MHz 5.56 MHz -- 8.33 MHz 4.17 MHz -- Direct Mode Bus clock 3.70 MHz 1.85 MHz -- 2.08 MHz 1.04 MHz --
The configuration of the clock generator is shown below.
CMODE PLL synthesizer 1/2 1/6 PFD Phase comparator 1/2 CPU clock 142.8 MHz VCO 1/8
X1 OSC X2 fB
PMC x1 x1/2 x1/4
Bus clock
Direct clock PMR.DPM fB: Oscillation frequency or external clock frequency
: Bus clock
OSC: Oscillator PFD: Phase Frequency Detector VCO: Voltage Controlled Oscillator PMC: Power Management Controller
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Data Sheet U13675EJ2V1DS00
PD705102
13. STANDBY FUNCTION
The V832 has the following two modes as standby functions: * Power management mode * Standby mode (1) Power management mode The following two power management modes can be used. According to the combination of these modes, the operating frequency is actively changed. * PLL mode This is the mode normally used. In this mode, the oscillation clock of the external input clock/OSC, which is expanded 6 or 8 times by the PLL synthesizer, is employed as the CPU clock. * Direct mode In this mode, the oscillation clock of the external input clock/OSC is employed as the CPU clock without passing through the PLL synthesizer. (2) Standby mode The following two standby modes can be used. * HALT mode In this mode, the clock generator (oscillator and PLL synthesizer) operates, but the operating clock of the CPU is stopped. The other internal peripheral functions are supplied with the clock and continue operation. By using this mode in combination with the normal mode, the power consumption of the entire system can be reduced. * STOP mode This mode stops supply of the clock to the CPU and peripheral I/O. It can reduce the power consumption much more than the HALT mode. Clock output of PLL synthesizer * In PLL mode: Operation of the PLL can be started or stopped by the PLLSS bit of the power management register (PMR). * In direct mode: The PLL always stops. Table 13-1 shows the operation of the clock generator in each mode.
Data Sheet U13675EJ2V1DS00
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PD705102
Table 13-1. Operation of Clock Generator by Standby Control
Modes Power Management Mode PLL mode Standby Mode Normal HALT STOP Direct mode Normal HALT STOP x x x x x x x x x Oscillator (OSC) PLL Synthesizer Clock Supply to Peripheral I/O Clock Supply to CPU
Remark
: Operates x: Stops : Operates or stops depending on setting Table 13-2. Operating Status in HALT/STOP Mode
Function HALT ModeNote 1 Operates OperatesNote 2 Operates Stops Retained Operates Stops StopsNote 3 Stops STOP Mode
Oscillator PLL synthesizer Bus clock CPU Port output Peripheral function Internal data A1 to A23 D0 to D31 BCYST CS0 to CS7 IORD, IOWR MRD, MWR, LLBEN, LUBEN, ULBEN, UUBEN LLDQM, LUDQM, ULDQM, UUDQM RAS, CAS, WE CKE R/W HLDRQ CLKOUT, SDCLKOUT STOPAK
Internal data such as registers of CPU retain status before HALT mode is set. Undefined High impedance when HLDAK = 0 High impedance 1 High impedance when HLDAK = 0 1 Undefined
0Note 4 1Note 5 1Note 6 Retained Operates
Self refreshNote 7
Retained Not accepted
Clock output (if clock output is not disabled) 0 1 0
Notes 1. Each pin is in the operating status during DMA transfer. 2 Stops in the direct mode. 3. Occasionally operates in PLL mode. 4. After reset, 1 till first SDRAM access. 5. When auto refresh is not executed. 6. 0 in the power down mode. 7. When refresh is prohibited, self refresh cannot be performed. In that case, this pin retains the status before the STOP mode.
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Data Sheet U13675EJ2V1DS00
PD705102
14. RESET/NMI CONTROL FUNCTION
The features of the reset/NMI control function are as follows: * RESET and NMI pins have a noise rejection circuit that samples the clock. * Performs forced reset, reset mask, and NMI mask processing from debug control unit Table 14-1 shows the status of the output pins during the system reset period and immediately after reset. This status is retained during the reset period. Table 14-1. Status of Output Pin Immediately after Reset
Function A1 to A23 D0 to D31 CS0 to CS7 BCYST IORD, IOWR WE, RAS, CAS, CKE LLBEN, LUBEN, ULBEN, UUBEN LLDQM, LUDQM, ULDQM, UUDQM R/W MRD, MWR CLKOUT, SDCLKOUT HLDAK Undefined High impedance 1 1 1 1 1 1 1 1 Clock output 1 Operating Status
PORT0 to PORT4Note, PORTA0 to PORTA7Note, PORTB0 to PORTB7Note High impedance DDO TRCDATA0 to TRCDATA3 STOPAK/TC Undefined Undefined 1
Note Pins with alternate functions as ports serve as port pins immediately after reset.
Data Sheet U13675EJ2V1DS00
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PD705102
15. INSTRUCTIONS
15.1 Instruction Format The V832 uses two instruction formats: 16-bit and 32-bit. The 16-bit instructions include binary operation, control, and conditional branch instructions, while the 32-bit instructions include load/store and I/O operation instructions, instructions for handling 16 bits of immediate data, and jump-and-link instructions. Some instructions contain unused fields, which must be fixed to 0, which are provided for future use. When an instruction is actually loaded into memory, its configuration is as follows: * Low-order part of each instruction format (including bit 0) Low-order address * High-order part of each instruction format (including bit 15 or 31) High-order address (1) reg-reg instruction format [FORMAT I] This instruction format has a 6-bit operation code field and two general-purpose register designation fields for operand specification, giving a total length of 16 bits.
15 opcode
10 9 reg 2
54 reg 1
0
(2) imm-reg instruction format [FORMAT II] This instruction format has a 6-bit operation code field, a 5-bit immediate data field, and a general-purpose register designation field, giving a total length of 16 bits.
15 opcode
10 9 reg 2
54 imm 5
0
(3) Conditional branch instruction format [FORMAT III] This instruction format has a 3-bit operation code field, a 4-bit condition code field, a 9-bit branch displacement field (bit 0 is handled as 0 and need not be specified), and a 1-bit sub-operation code, giving a total length of 16 bits.
15
13 12 cond
98 disp 9
10 s s = 0: Bcond s = 1: ABcond
opcode
s: sub-opcode
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Data Sheet U13675EJ2V1DS00
PD705102
(4) Medium-distance jump instruction format [FORMAT IV] This instruction format has a 6-bit operation code field and a 26-bit displacement field (the lowest-order bit must be 0), giving a total length of 32 bits.
15 opcode 10 9 0 31 disp 26 16 0
(5) Three-operand instruction format [FORMAT V] This instruction format has a 6-bit operation code field, two general-purpose register designation fields, and a 16-bit immediate data field, giving a total length of 32 bits.
15 opcode 10 9 reg 2 54 reg 1 0 31 imm 16 16
(6) Load/store instruction format [FORMAT VI] This instruction format has a 6-bit operation code field, two general-purpose register designation fields, and a 16-bit displacement field, giving a total length of 32 bits.
15 opcode 10 9 reg 2 54 reg 1 0 31 disp 16 16
(7) Extended instruction format [FORMAT VII] This instruction format has a 6-bit operation code field, two general-purpose register designation fields, and a 6-bit sub-operation code field, giving a total length of 32 bits.
15 opcode 10 9 reg 2 54 reg 1 0 31 sub-opcode 26 25 RFU 16
(8) Three-register operand instruction format [FORMAT VIII] This instruction format has a 6-bit operation code field, three general-purpose register designation fields, and a 6-bit sub-operation code field, giving a total length of 32 bits.
15 opcode 10 9 reg 2 54 reg 1 0 31 sub-opcode 26 25 RFU 21 20 reg 3 16
(9) No-operand instruction format [FORMAT IX] This instruction format has a 6-bit operation code field and a 1-bit sub-operation code field, giving a total length of 16 bits.
15 opcode s: sub-opcode 10 9 RFU 10 s
Data Sheet U13675EJ2V1DS00
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PD705102
15.2 Instructions (Listed Alphabetically) The instructions are listed below in alphabetic order of their mnemonics.
Explanation of list format Instruction ADD Operand(s) reg1, reg2 Format CY OV I * * S * Z * Function
Instruction mnemonic
Instruction Indicates how each flag changes. format --: Does not change. (See 15.1 Instruction Format) *: Changes. 0: Becomes 0. 1: Becomes 1.
Abbreviations of operands Abbreviation reg1 reg2 Meaning General-purpose register (used as a source register) General-purpose register (used mainly as a destination register, but in some instructions, used as a source register) General-purpose register (used mainly as a destination register, but in some instructions, used as a source register) x bits of immediate data x-bit displacement System register number Trap handler address corresponding to trap vector
reg3 immx dispx regID vector adr
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Data Sheet U13675EJ2V1DS00
PD705102
Instruction ABC ABE ABGE ABGT ABH ABL ABLE ABLT ABN ABNC ABNE ABNH ABNL ABNV ABNZ ABP ABR ABV ABZ ADD Operand(s) disp9 disp9 disp9 disp9 disp9 disp9 disp9 disp9 disp9 disp9 disp9 disp9 disp9 disp9 disp9 disp9 disp9 disp9 disp9 reg1, reg2 imm5, reg2 ADDI imm16, reg1, reg2 Format III III III III III III III III III III III III III III III III III III III I II V CY -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- * * * OV -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- * * * S -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- * * * Z -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- * * * Function High-speed conditional branch (if Carry) relative to PC. High-speed conditional branch (if Equal) relative to PC. High-speed conditional branch (if Greater than or Equal) relative to PC. High-speed conditional branch (if Greater than) relative to PC. High-speed conditional branch (if Higher) relative to PC. High-speed conditional branch (if Lower) relative to PC. High-speed conditional branch (if Less than or Equal) relative to PC. High-speed conditional branch (if Less than) relative to PC. High-speed conditional branch (if Negative) relative to PC. High-speed conditional branch (if Not Carry) relative to PC. High-speed conditional branch (if Not Equal) relative to PC. High-speed conditional branch (if Not Higher) relative to PC. High-speed conditional branch (if Not Lower) relative to PC. High-speed conditional branch (if Not Overflow) relative to PC. High-speed conditional branch (if Not Zero) relative to PC. High-speed conditional branch (if Positive) relative to PC. High-speed unconditional branch (Always) relative to PC. High-speed conditional branch (if Overflow) relative to PC. High-speed conditional branch (if Zero) relative to PC. Addition. reg1 is added to reg2 and the sum is written into reg2. Addition. imm5, sign-extended to a word, is added to reg2 and the sum is written into reg2. Addition. imm16, sign-extended to a word, is added to reg1, and the sum is written into reg2.
Data Sheet U13675EJ2V1DS00
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PD705102
Instruction AND ANDI Operand(s) reg1, reg2 imm16, reg1, reg2 disp9 [reg1], [reg2] [reg2], [reg1] disp9 disp9 disp9 disp9 [reg1], [reg2] [reg2], [reg1] disp9 disp9 disp9 disp9 disp9 disp9 disp9 disp9 disp9 disp9 disp9 disp9 I V Format CY -- -- OV 0 0 S * 0 Z * * Function AND. reg2 and reg1 are ANDed and the result is written into reg2. AND. reg1 is ANDed with imm16, zero-extended to a word, and result is written into reg2. Conditional branch (if Carry) relative to PC. Block transfer. 4 words of data are transferred from external memory to on-chip data RAM. Block transfer. 4 words of data are transferred from on-chip data RAM to external memory. Conditional branch (if Equal) relative to PC. Conditional branch (if Greater than or Equal) relative to PC. Conditional branch (if Greater than) relative to PC. Conditional branch (if Higher) relative to PC. Block transfer. 4 words of data are transferred from external memory to on-chip instruction RAM. Block transfer. 4 words of data are transferred from on-chip instruction RAM to external memory. Conditional branch (if Lower) relative to PC. Conditional branch (if Less than or Equal) relative to PC. Conditional branch (if Less than) relative to PC. Conditional branch (if Negative) relative to PC. Conditional branch (if Not Carry) relative to PC. Conditional branch (if Not Equal) relative to PC. Conditional branch (if Not Higher) relative to PC. Conditional branch (if Not Lower) relative to PC. Conditional branch (if Not Overflow) relative to PC. Conditional branch (if Not Zero) relative to PC. Conditional branch (if Positive) relative to PC. Unconditional branch (Always) relative to PC. Return from fatal exception handling. Conditional branch (if Overflow) relative to PC. Conditional branch (if Zero) relative to PC. Inter-processor synchronization in multiprocessor system.
BC BDLD BDST BE BGE BGT BH BILD BIST BL BLE BLT BN BNC BNE BNH BNL BNV BNZ BP BR BRKRET BV BZ CAXI
III VII VII III III III III VII VII III III III III III III III III III III III III IX
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- *
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- *
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- *
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- *
disp9 disp9 disp16[reg1], reg2
III III VI
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Data Sheet U13675EJ2V1DS00
PD705102
Instruction CMP Operand(s) reg1, reg2 I Format CY * OV * S * Z * Function Comparison. reg2 is compared with reg1 sign-extended to a word and the condition flag is set according to the result. The comparison involves subtracting reg1 from reg2. Comparison. reg2 is compared with imm5 sign-extended to a word and the condition flag is set according to the result. The comparison involves subtracting imm5, sign-extended to a word, from reg2. Disable interrupt. Maskable interrupts are disabled. DI instruction cannot disable non-maskable interrupts. Division of signed operands. reg2 is divided by reg1 (signed operands). The quotient is stored in reg2 and the remainder in r30. The division is performed so that the sign of the remainder will match that of the dividend. Division of unsigned operands. reg2 is divided by reg1 (unsigned operands). The quotient is stored in reg2 and the remainder in r30. The division is performed so that the sign of the remainder will match that of the dividend. Enable interrupt. Maskable interrupts are enabled. EI instruction cannot enable non-maskable interrupts. HALT IN.B disp16[reg1], reg2 IX VI -- -- -- -- -- -- -- -- Processor halt. The processor is placed in sleep mode. Port input. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit port address. A byte of data is read from the resulting port address, zero-extended to a word, then stored in reg2. Port input. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit port address. A halfword of data is read from the generated port address, zero-extended to a word, and stored in reg2. Bit 0 of the unsigned 32-bit port address is masked to 0. Port input. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit port address. A word of data is read from the resulting port address, then written into reg2. Bits 0 and 1 of the unsigned 32-bit port address are masked to 0.
imm5, reg2
II
*
*
*
*
DI
II
--
--
--
--
DIV
reg1, reg2
I
--
*
*
*
DIVU
reg1, reg2
I
--
0
*
*
EI
II
--
--
--
--
IN.H
disp16[reg1], reg2
VI
--
--
--
--
IN.W
disp16[reg1], reg2
VI
--
--
--
--
Data Sheet U13675EJ2V1DS00
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PD705102
Instruction JAL Operand(s) disp26 Format IV CY -- OV -- S -- Z -- Function Jump and link. The sum of the current PC and 4 is written into r31. disp26, sign-extended to a word, is added to the PC and the sum is set to the PC for control transfer. Bit 0 of disp26 is masked. Indirect unconditional branch via register. Control is passed to the address designated by reg1. Bit 0 of the address is masked to 0. Unconditional branch. disp26, sign-extended to a word, is added to the current PC and control is passed to the address specified by that sum. Bit 0 of disp26 is masked to 0. Byte load. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit address. A byte of data is read from the generated address, sign-extended to a word, then written into reg2. Halfword load. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit address. A halfword of data is read from the generated address, sign-extended to a word, then written into reg2. Bit 0 of the unsigned 32-bit address is masked to 0. Word load. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit address. A word of data is read from the generated address, then written into reg2. Bits 0 and 1 of the unsigned 32-bit address are masked to 0. LDSR reg2, regID II * * * * Load into system register. The contents of reg2 are set in the system register identified by the system register number (regID). Saturation operation on signed 32-bit operands. reg1 and reg2 are multiplied together as signed integers and the product is added to reg3. [If no overflow has occurred:] The result is stored in reg3. [If an overflow has occurred:] The SAT bit is set. If the result is positive, the positive maximum is written into reg3; if the result is negative, the negative maximum is written into reg3.
JMP
[reg1]
I
--
--
--
--
JR
disp26
IV
--
--
--
--
LD.B
disp16[reg1], reg2
VI
--
--
--
--
LD.H
disp16[reg1], reg2
VI
--
--
--
--
LD.W
disp16[reg1], reg2
VI
--
--
--
--
MAC3
reg1, reg2, reg3
VIII
--
--
--
--
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Data Sheet U13675EJ2V1DS00
PD705102
Instruction MACI Operand(s) imm16, reg1, reg2 Format V CY -- OV -- S -- Z -- Function Saturation operation on signed 32-bit operands. reg1 and imm16, sign-extended to 32 bits, are multiplied together as signed integers and the product is added to reg2 as a signed integer. [If no overflow has occurred:] The result is written into reg2. [If an overflow has occurred:] The SAT flag is set. If the result is positive, the positive maximum is written into reg2; if the result is negative, the negative maximum is written into reg2. MACT3 reg1, reg2, reg3 VIII -- -- -- -- Sum-of-products operation on signed 32-bit operands. reg1 and reg2 are multiplied together as signed integers and the high-order 32 bits of the product are added to reg3 as signed integers. [If no overflow has occurred:] The result is written into reg3. [If an overflow has occurred:] The SAT flag is set. If the result is positive, the positive maximum is written into reg3; if the result is negative, the negative maximum is written into reg3. MAX3 reg1, reg2, reg3 reg1, reg2, reg3 reg1, reg2, imm5, reg2 MOVEA imm16, reg1, reg2 imm16, reg1, reg2 reg1, reg2 VIII -- -- -- -- Maximum. reg2 and reg1 are compared as signed integers. The larger value is written into reg3. Minimum. reg2 and reg1 are compared as signed integers. The smaller value is written into reg3. Data transfer. reg1 is copied to reg2 for data transfer. II V -- -- -- -- -- -- -- -- Data transfer. imm5, sign-extended to a word, is copied into reg2 for data transfer. Addition. The high-order 16 bits (imm16), sign-extended to a word, are added to reg1 and the sum is written into reg2. Addition. A word of data consisting of the highorder 16 bits (imm16) and low-order 16 bits (0) is added to reg1 and the sum is written into reg2. Multiplication of signed operands. reg2 and reg1 are multiplied together as signed values. The high-order 32 bits of the product (double word) are written into r30 and low-order 32 bits are written into reg2. Multiplication of signed 32-bit operands. reg2 and reg1 are multiplied together as signed integers. The high-order 32 bits of the product are written into reg3.
MIN3
VIII
--
--
--
--
MOV
I
--
--
--
--
MOVHI
V
--
--
--
--
MUL
I
--
*
*
*
MUL3
reg1, reg2, reg3
VIII
--
--
--
--
Data Sheet U13675EJ2V1DS00
43
PD705102
Instruction MULI Operand(s) imm16, reg1, reg2 Format V CY -- OV -- S -- Z -- Function Saturation multiplication of signed 32-bit operands. reg1 and imm16, sign-extended to 32 bits, are multiplied together as signed integers. [If no overflow has occurred:] The result is written into reg2. [If an overflow has occurred:] The SAT flag is set. If the result is positive, the positive maximum is written into reg2; if the result is negative, the negative maximum is written into reg2. MULT3 reg1, reg2, reg3 VIII -- -- -- -- Saturation multiplication of signed 32-bit operands. reg1 and reg2 are multiplied together as signed integers. The high-order 32 bits of the product are written into reg3. Multiplication of unsigned operands. reg1 and reg2 are multiplied together as unsigned values. The high-order 32 bits of the product (double word) are written into r30 and the low-order 32 bits are written into reg2. No operation. NOT. The NOT (one's complement) of reg1 is taken and written into reg2. OR. The OR of reg2 and reg1 is taken and written into reg2. OR. The OR of reg1 and imm16, zeroextended to a word, is taken and written into reg2. OUT.B reg2, disp16[reg1] VI -- -- -- -- Port output. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit port address. The low-order one byte of the data in reg2 is output to the resulting port address. Port output. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit port address. The low-order two bytes of the data in reg2 are output to the resulting port address. Bit 0 of the unsigned 32-bit port address is masked to 0. Port output. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit port address. The word of data in reg2 is output to the produced port address. Bits 0 and 1 of the unsigned 32-bit port address are masked to 0. Return from trap/interrupt handling routine. The return PC and PSW are read from the system registers so that program execution will return from the trap or interrupt handling routine.
MULU
reg1, reg2
I
--
*
*
*
NOP NOT OR ORI reg1, reg2 reg1, reg2 imm16, reg1, reg2
III I I V
-- -- -- --
-- 0 0 0
-- * * *
-- * * *
OUT.H
reg2, disp16[reg1]
VI
--
--
--
--
OUT.W
reg2, disp16[reg1]
VI
--
--
--
--
RETI
IX
*
*
*
*
44
Data Sheet U13675EJ2V1DS00
PD705102
Instruction SAR Operand(s) reg1, reg2 I Format CY * OV 0 S * Z * Function Arithmetic right shift. reg2 is arithmetically shifted to the right by the displacement specified by the low-order five bits of reg1 (MSB value is copied to the MSB in sequence). The result is written into reg2. Arithmetic right shift. reg2 is arithmetically shifted to the right by the displacement specified by imm5, zero-extended to a word. The result is written into reg2. Saturation addition. reg1 and reg2 are added together as signed integers. [If no overflow has occurred:] The result is written into reg3. [If an overflow has occurred:] The SAT flag is set. If the result is positive, the positive maximum is written into reg3; if the result is negative, the negative maximum is written into reg3. SATSUB3 reg1, reg2, reg3 VIII * * * * Saturation subtraction. reg1 is subtracted from reg2 as signed integers. [If no overflow has occurred:] The result is written into reg3. [If an overflow has occurred:] The SAT flag is set. If the result is positive, the positive maximum is written into reg3; if the result is negative, the negative maximum is written into reg3. SETF imm5, reg2 II -- -- -- -- Set flag condition. reg2 is set to 1 if the condition specified by the low-order four bits of imm5 matches the condition flag; otherwise it is set to 0. SHL reg1, reg2 I * 0 * * Logical left shift. reg2 is logically shifted to the left (0 is put on the LSB) by the displacement specified by the low-order five bits of reg1. The result is written into reg2. Logical left shift. reg2 is logically shifted to the left by the displacement specified by imm5, zero-extended to a word. The result is written into reg2. Left shift of concatenation. The 64 bits consisting of reg3 (high order) and reg2 (low order) are logically shifted to the left by the displacement specified by the low-order five bits of reg1. The high-order 32 bits of the result are written into reg3.
imm5, reg2
II
*
0
*
*
SATADD3
reg1, reg2, reg3
VIII
*
*
*
*
imm5, reg2
II
*
0
*
*
SHLD3
reg1, reg2, reg3
VIII
--
--
--
--
Data Sheet U13675EJ2V1DS00
45
PD705102
Instruction SHR Operand(s) reg1, reg2 I Format CY * OV 0 S * Z * Function Logical right shift. reg2 is logically shifted to the right by the displacement specified by the low-order five bits of reg1 (0 is put on the MSB). The result is written into reg2. Logical right shift. reg2 is logically shifted to the right by the displacement specified by imm5, zero-extended to a word. The result is written into reg2. Right shift of concatenation. The 64 bits consisting of reg3 (high order) and reg2 (low order) are logically shifted to the right by the displacement specified by the low-order five bits of reg1. The low-order 32 bits of the result are written into reg3. Byte store. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit address. The low-order one byte of data in reg2 is stored at the resulting address. Halfword store. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit address. The low-order two bytes of the data in reg2 are stored at the resulting address. Bit 0 of the unsigned 32-bit address is masked to 0. Word store. disp16, sign-extended to a word, is added to reg1 to generate an unsigned 32-bit address. The word of data in reg2 is stored at the resulting address. Bits 0 and 1 of the unsigned 32-bit address are masked to 0. STBY STSR regID, reg2 IX II -- -- -- -- -- -- -- -- Processor stop. The processor is placed in stop mode. System register store. The contents of the system register identified by the system register number (regID) are set in reg2. Subtraction. reg1 is subtracted from reg2. The difference is written into reg2. Software trap. The return PC and PSW are saved in the system registers: PSW.EP = 1 Save in FEPC, FEPSW PSW.EP = 0 Save in EIPC, EIPSW The exception code is set in the ECR: PSW.EP = 1 Set in FECC PSW.EP = 0 Set in EICC PSW flags are set: PSW.EP = 1 Set NP and ID PSW.EP = 0 Set EP and ID Program execution jumps to the trap handler address corresponding to the trap vector (0-31) specified by vector and begins exception handling.
imm5, reg2
II
*
0
*
*
SHRD3
reg1, reg2, reg3
VIII
--
--
--
--
ST.B
reg2, disp16[reg1]
VI
--
--
--
--
ST.H
reg2, disp16[reg1]
VI
--
--
--
--
ST.W
reg2, disp16[reg1]
VI
--
--
--
--
SUB TRAP
reg1, reg2 vector
I II
* --
* --
* --
* --
46
Data Sheet U13675EJ2V1DS00
PD705102
Instruction XOR XORI Operand(s) reg1, reg2 imm16, reg1, reg2 I V Format CY -- -- OV 0 0 S * * Z * * Function Exclusive OR. The exclusive OR of reg2 and reg1 is taken and written into reg2. Exclusive OR. The exclusive OR of reg1 and imm16, zero-extended to a word, is taken and written into reg2.
Data Sheet U13675EJ2V1DS00
47
PD705102
16. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter 3.3-V operation supply voltage 2.5-V operation supply voltage Symbol VDDO VDDI VDDPLL Input voltageNote VI VDDO 3.7 V VDDO < 3.7 V Clock input voltage Operating ambient temperature VK TA Conditions Ratings -0.5 to +4.0 -0.5 to +3.6 -0.5 to +3.6 -0.5 to +4.0 -0.5 to VDDO + 0.3 -0.5 to VDDO + 0.3 V C C C C Unit V V V V
PD705102-143 CPU core frequency 143 MHz
CPU core frequency 144 MHz
-40 to +85 -40 to +70 -40 to +85 -65 to +150
PD705102-133 CPU core frequency 133 MHz
Storage temperature Tstg
Note Includes output pins. Cautions 1. Do not directly connect the output (or input/output) pins of an IC device to each other, and do not connect them directly to the VDD, VCC or GND. However, these restrictions do not apply to the high-impedance pins of an external circuit, whose timing has been specifically designed to avoid output collision. 2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. For IC products, normal operation and quality are guaranteed only when the ratings and conditions described under the DC and AC characteristics are satisfied. Operating Conditions
Parameter 3.3-V operation supply voltage 2.5-V operation supply voltage Operating ambient temperature Symbol VDDO VDDI TA Conditions MIN. 3.0 2.3 MAX. 3.6 2.7 +85 +70 +85 Unit V V C C C
PD705102-143 CPU core frequency 143 MHz
CPU core frequency 144 MHz
-40 -40 -40
PD705102-133 CPU core frequency 133 MHz
Caution V832 has two types of power supply, and there are no restrictions on the order that the voltage is to be applied. However, be sure not to keep a status whereby only one power supply is applied voltage for 1 second or more.
48
Data Sheet U13675EJ2V1DS00
PD705102
DC Characteristics (VDDO = 3.0 to 3.6 V, VDDI = 2.3 to 2.7 V)
PD705102-143 (CPU core frequency 143 MHz): TA = -40 to +85C PD705102-143 (CPU core frequency 144 MHz): TA = -40 to +70C PD705102-133:
Parameter Clock input voltage, low Clock input voltage, high Input voltage, low Input voltage, high Schmitt input voltage, low Schmitt input voltage, high Output voltage, low Output voltage, high Input leakage current, low Input leakage current, high Output leakage current, low Output leakage current, high Supply currentNote 3 2.5 V Symbol VKL VKH VIL VIH VSL VSH VOL VOH ILIL ILIH ILOL ILOH IDDI Note 2 Note 2 IOL = 3.2 mA IOH = -400 A VIN = 0 V VIN = VDDO VO = 0 V VO = VDDO In normal operation Clock division ratio 1/1 (PLL mode) Clock division ratio 1/2 Clock division ratio 1/4 In normal operation Clock division ratio 1/1 (Direct mode) In HALT mode In STOP modeNote 4 3.3 V IDDO In normal operation Clock division ratio 1/1 (PLL mode) Clock division ratio 1/2 Clock division ratio 1/4 In normal operation Clock division ratio 1/1 (Direct mode) In HALT mode In STOP modeNote 4 Clock division ratio 1/2 Clock division ratio 1/2 115 60 33 15 7.5 20 25 19 10 6 4 3 12 5 20 10 29 450 28 0.85 VDDO -10 10 -10 10 160 Note 1 Note 1 Conditions
TA = -40 to +85C
MIN. -0.5 0.8 VDDO -0.5 2.0 -0.5 0.8 VDDO TYP. MAX. +0.2 VDDO VDDO + 0.3 +0.6 VDDO + 0.3 +0.2 VDDO VDDO + 0.3 0.4 Unit V V V V V V V V
A A A A
mA mA mA mA mA mA
A
mA mA mA mA mA mA
A
Notes 1. X2 pin, DCK pin, and SCLK pin at external clock input 2. PORT0/SCLK, PORT2/SI, PORT3/RXD 3. Supply current at input clock: 17.85 MHz with output pins open, PLL 8x 4. External clock mode when clock input is stopped. Capacitance
Parameter Input capacitance I/O capacitance Symbol CI CIO fC = 1 MHz Conditions MIN. MAX. 10 10 Unit pF pF
Remark These parameters are sample values, not the value actually measured.
Data Sheet U13675EJ2V1DS00
49
PD705102
AC Characteristics (VDDO = 3.0 to 3.6 V, VDDI = 2.3 to 2.7 V, CL = 50 pF)
PD705102-143 (CPU core frequency 143 MHz): TA = -40 to +85C PD705102-143 (CPU core frequency 144 MHz): TA = -40 to +70C PD705102-133 :
AC test input waveform
VDDO 2.0 V 0.5 VDDO 0V
4 ns
TA = -40 to +85C
Test point 0.6 V
AC test output waveform (a) CS0, CS1, WE, RAS, UUDQM, ULDQM, LUDQM, LLDQM, CKE, CAS, SDCLKOUT, CLKOUT, A1 to A23, D0 to D31
VDDO 0.5 VDDO 0V Test point 0.4 V
0.85 VDDO
(b) Other than above (a)
VDDO 1.4 V 0V Test point 0.4 V
0.85 VDDO
Test load
V832 output pin CL = 50 pF
50
Data Sheet U13675EJ2V1DS00
PD705102
(1) Clock input (X2) timing (when external clock input used) * PD705102-143
Parameter Symbol Conditions PLL Magnification x6 mode MIN. External clock cycle <1> tCYX Note 1 Note 2 Note 3 Note 4 External clock high-level time <2> tXXH Note 1 Note 3 External clock low-level time <3> tXXL Note 1 Note 3 External clock rise time External clock fall time <4> <5> tXR tXF 16 15.8 16 15.8 5 5 41.6 42 MAX. 60 45 60 45 23 22.75 23 22.75 5 5 55.5 x8 mode MIN. 56 MAX. 80 60 80 60 ns ns ns ns ns ns ns ns ns ns Unit
Notes 1. TA = -40 to +85C, when other than 1/4 is selected as the division ratio of the input clock (CPU core frequency (when defaulted) = 100 to 143 MHz) 2. TA = -40 to +85C, when 1/4 is selected as the division ratio of the input clock (CPU core frequency = 33.3 to 35.8 MHz) 3. TA = -40 to +70C, when other than 1/4 is selected as the division ratio of the input clock (CPU core frequency (when defaulted) = 100 to 144 MHz) 4. TA = -40 to +70C, when 1/4 is selected as the division ratio of the input clock (CPU core frequency = 33.3 to 36 MHz) Remark The stability of the input clock is 0.1% of tCYX or lower. * PD705102-133
Parameter Symbol Conditions PLL Magnification x6 mode MIN. External clock cycle <1> tCYX Note 1 Note 2 External clock high-level time External clock low-level time External clock rise time External clock fall time <2> <3> <4> <5> tXXH tXXL tXR tXF 17.5 17.5 5 5 45 MAX. 60 45 25 25 5 5 x8 mode MIN. 60 MAX. 80 60 ns ns ns ns ns ns Unit
Notes 1. TA = -40 to +85C, when other than 1/4 is selected as the division ratio of the input clock (CPU core frequency (when defaulted) = 100 to 133 MHz) 2. TA = -40 to +85C, when 1/4 is selected as the division ratio of the input clock (CPU core frequency = 33.3 MHz) Remark The stability of the input clock is 0.1% of tCYX or lower.
<1> <2> 0.8 VDDO X2 (input) 1.4 V 0.2 VDDO <3>
Data Sheet U13675EJ2V1DS00
<5>
<4>
51
PD705102
(2) Clock output timing (CLKOUT, SDCLKOUT)
Parameter Symbol Conditions PLL Magnification x6 mode MIN. External clock cycle <6> tCYK Note 1 Note 2 Note 3 External clock high-level time External clock low-level time External clock rise time External clock fall time <7> <8> <9> tKKH tKKL tKR 21 20.8 22.5 tCYK/2 - 5 tCYK/2 - 5 5 5 MAX. x8 mode MIN. 28 27.75 30 tCYK/2 - 5 tCYK/2 - 5 5 5 MAX. ns ns ns ns ns ns ns Unit
<10> tKF
Notes 1. PD705102-143, TA = -40 to +85C 2. PD705102-143, TA = -40 to +70C 3. PD705102-133, TA = -40 to +85C
<6> <7> 0.8 VDDO 1.4 V CLKOUT (output) SDCLKOUT (output) 0.2 VDDO <8> <10> <9>
52
Data Sheet U13675EJ2V1DS00
PD705102
(3) Reset timing
Parameter RESET hold time (from VDDI VALID) RESET setup time (to CLKOUT) Symbol <11> <12> tHVR tSRK tHKR tWRL Note 1 Note 2 Note 3 7 7 20 10 15 x tCYX Conditions MIN. MAX. 2 Unit
s
ns ns ms ms ns
RESET hold time (from CLKOUT) <13> RESET pulse low-level width <14>
Notes 1. At power on or when returned from STOP mode, and the internal clock is generated. 2. At power on or when returned from STOP mode, and the external clock is generated, after clock has stabilized. 3. When clock has stabilized under conditions other than Notes 1 and 2. Remark It is not necessary to satisfy tSRK and tHKR if reset during the period of tHVR. In such a case, however, the reset acknowledge timing may be shifted.
VDDI
0.9 VDDI <11> <12>
CLKOUT (output) <13> RESET (input) <14> <12>
Data Sheet U13675EJ2V1DS00
53
PD705102
(4) SDRAM access timing
Parameter BCYST delay time (from SDCLKOUT) Address delay time (from SDCLKOUT) RAS delay time (from SDCLKOUT) CAS delay time (from SDCLKOUT) CS0, CS1 delay time (from SDCLKOUT) WE delay time (from SDCLKOUT) R/W delay time (from SDCLKOUT) xxDQM delay time (from SDCLKOUT) CKE delay time (from SDCLKOUT) Data input setup time (SDRAM read, to SDCLKOUT) Data input hold time (SDRAM read, from SDCLKOUT) Data output delay time (from active, from SDCLKOUT) Data output delay time (from float, from SDCLKOUT) Data float delay time (from SDCLKOUT) <27> <28> tLZKDT tHZKDT 2 3 12.5 20 ns ns Symbol <15> <16> <17> <18> <19> <20> <21> <22> <23> <24> <25> <26> tDKBC tDKA tDKRAS tDKCAS tDKCS tDKWE tDKRW tDKDQM tDKCKE tSDRMK tHKDRM tDKDT Conditions MIN. 2 2 2 2 2 2 2 2 2 5 2 2 12.5 MAX. 12.5 12.5 12.5 12.5 12.5 12.5 12.5 12.5 12.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns
Remark xxDQM: LLDQM, LUDQM, ULDQM, UUDQM
54
Data Sheet U13675EJ2V1DS00
PD705102
SDRAM single read cycle (off-page) (TRP = 0, TRCD = 0): with 32-bit data bus
Tpr SDCLKOUT (output)
Tac
Tr1
Tra2
Tra3
Tri
Ti
Command <15> BCYST (output) CKE (output) CS0, CS1 (output) <17> RAS (output) <18> CAS (output) <20> WE (output) <16> Bank address (output) <16> A12 (output) <16> Address (output) H
PRE
ACT <15>
RD <15> <15>
<19>
<19>
<19>
<17>
<17>
<18>
<18>
<18>
<20>
<20>
<16> BA <16> RA <16> RA <16> CA <24> <25> <16> <16> <16>
<16>
<16>
<16>
D0 to D31 (input) <21> R/W (output) <22> xxDQM (output) <22> <21>
Remarks 1. The broken lines indicate high impedance. 2. xxDQM: LLDQM, LUDQM, ULDQM, UUDQM
Data Sheet U13675EJ2V1DS00
55
PD705102
SDRAM single read cycle (on-page): with 32-bit data bus
Tr1s SDCLKOUT (output) Tra2 Tra3 Tri Ti
Command <15> BCYST (output) H <19>
RD <15> <15>
CKE (output)
<19>
<19>
CS0, CS1 (output) <17> RAS (output) <18> CAS (output) <20> WE (output) <16> Bank address (output) <16> A12 (output) <16> Address (output) CA <24> <25> D0 to D31 (input) <21> R/W (output) <22> xxDQM (output) <22> <21> <16> <16> BA <16> <16> <16> <16> <20> <18> <18>
Remarks 1. The broken lines indicate high impedance. 2. xxDQM: LLDQM, LUDQM, ULDQM, UUDQM
56
Data Sheet U13675EJ2V1DS00
PD705102
SDRAM burst read cycle (off-page) (TRP = 0, TRCD = 0): with 32-bit data bus
Tpr Tac Tr1 Trb2 Trb3 Trb4 Trb5 Trb6 Tri Ti
SDCLKOUT (output)
Command
PRE <15>
ACT
RD
RD
RD
RD <15> <15>
<15>
BCYST (output) H <19> <19> <19>
CKE (output)
CS0, CS1 (output) <17> RAS (output) <18> CAS (output) <20> WE (output) <16> Bank address (output) <16> A12 (output) <16> A1 to A23 (output) <16> <16> <16> RA <16> RA <16> CA <16> CA <16> CA <24> <25> D0 to D31 (input) <21> R/W (output) 1 2 <24> <25> <16> CA <24> <25> 3 4 <24> <25> <21> <16> BA <16> <16> <16> <16> <20> <20> <18> <18> <18> <17> <17>
xxDQM (output)
L
Remarks 1. The broken lines indicate high impedance. 2. xxDQM: LLDQM, LUDQM, ULDQM, UUDQM
Data Sheet U13675EJ2V1DS00
57
PD705102
SDRAM burst read cycle (on-page): with 32-bit data bus
Tr1s SDCLKOUT (output) Trb2 Trb3 Trb4 Trb5 Trb6 Tri Ti
Command
RD <15>
RD
RD
RD <15> <15>
BCYST (output) CKE (output) CS0, CS1 (output) <17> RAS (output) <18> CAS (output) <20> WE (output) <16> Bank address (output) <16> A12 (output) <16> Address (output) CA <16> CA <16> CA <16> CA <24> <25> D0 to D31 (input) <21> R/W (output) <24> <25> <24> <25> <21> <24> <25> <16> <16> BA <16> <16> <16> <16> <20> <18> <18> H
<19>
<19>
<19>
xxDQM (output)
L
Remarks 1. The broken lines indicate high impedance. 2. xxDQM: LLDQM, LUDQM, ULDQM, UUDQM
58
Data Sheet U13675EJ2V1DS00
PD705102
SDRAM single write cycle (off-page) (TRP = 0, TRCD = 0): with 32-bit data bus
Tpr SDCLKOUT (output)
Tac
Tw1
Twi
Command
PRE <15>
ACT <15>
WR <15> <15>
BCYST (output) H
CKE (output)
<19>
<19>
CS0, CS1 (output) <17> RAS (output) <18> <18> CAS (output) <20> WE (output) <16> Bank address (output) <16> A12 (output) <16> Address (output) <16> RA <27> D0 to D31 (output) <21> R/W (output) <22> xxDQM (output) <22> <21> <16> RA <16> CA <28> <16> <16> BA <16> <16> <16> <16> <16> <20> <20> <20> <20> <18> <18> <17> <17>
Remarks 1. The broken lines indicate high impedance. 2. xxDQM: LLDQM, LUDQM, ULDQM, UUDQM
Data Sheet U13675EJ2V1DS00
59
PD705102
SDRAM single write cycle (on-page): with 32-bit data bus
Tw1s SDCLKOUT (output) Twi
Command <15> BCYST (output) H
WR <15> <15>
CKE (output)
<19>
<19>
CS0, CS1 (output) <17> RAS (output) <18> CAS (output) <20> WE (output) <16> Bank address (output) <16> A12 (output) <16> Address (output) <27> D0 to D31 (output) <21> R/W (output) <22> xxDQM (output) <22> <21> CA <28> <16> <16> BA <16> <16> <16> <16> <20> <20> <18> <18>
Remarks 1. The broken lines indicate high impedance. 2. xxDQM: LLDQM, LUDQM, ULDQM, UUDQM
60
Data Sheet U13675EJ2V1DS00
PD705102
SDRAM burst write cycle (off-page) (TRP = 0, TRCD = 0): with 32-bit data bus
Tpr Tac Tw1 Tw2 Tw3 Tw4
SDCLKOUT (output)
Command
PRE <15>
ACT
WR <15>
WR
WR
WR <15>
BCYST (output)
H
CKE (output) CS0, CS1 (output)
<19>
<19>
<17>
<17>
<17>
RAS (output)
<18> <18> <18>
CAS (output)
<20> <20> <20> <20>
WE (output)
<16> <16> BA <16> <16> RA <16> <16> RA <27> <16> CA <26> 1 <21> 2 <16> CA <26> 3 <21> <16> CA <26> 4 <16> <16> CA <28> <16> <16>
Bank address (output)
A12 (output)
Address (output)
D0 to D31 (output)
R/W (output)
xxDQM (output) L
Remarks 1. The broken lines indicate high impedance. 2. xxDQM: LLDQM, LUDQM, ULDQM, UUDQM
Data Sheet U13675EJ2V1DS00
61
PD705102
SDRAM burst write cycle (on-page): with 32-bit data bus
Tw1s SDCLKOUT (output)
Twr2
Tw3
Tw4
Command
WR <15>
WR
WR
WR <15>
BCYST (output) H <19> CS0, CS1 (output) <17> RAS (output) <18> CAS (output) <20> WE (output) <16> Bank address (output) <16> A12 (output) <16> Address (output) <27> D0 to D31 (output) <21> R/W (output) <21> CA <26> <16> CA <26> <16> CA <26> <16> CA <28> <16> BA <16> <16> <20> <18> <19>
CKE (output)
xxDQM (output) L
Remarks 1. The broken lines indicate high impedance. 2. xxDQM: LLDQM, LUDQM, ULDQM, UUDQM
62
Data Sheet U13675EJ2V1DS00
PD705102
Auto refresh cycle (TRP = 0): with 32-bit data bus
Tap SDCLKOUT (output) Trf
Command <15> BCYST (output)
PALL
REF
CKE (output)
H <19> <19>
CS0, CS1 (output) <17> RAS (output) <18> CAS (output) <20> WE (output) <16> Bank address (output) <16> A12 (output) <16> Address (output) xxDQM (output) <16> <16> <16> <16> <20> <20> <18> <18> <17>
L
Remark xxDQM: LLDQM, LUDQM, ULDQM, UUDQM
Data Sheet U13675EJ2V1DS00
63
PD705102
Self refresh cycle (TRP = 0): with 32-bit data bus
Tap
Tsr
Tsri
Tsri
SDCLKOUT (output) Command <15> BCYST (output) <23> CKE (output) <19> CS0, CS1 (output) <17> RAS (output) <18> CAS (output) <20> WE (output) <16> Bank address (output) <16> A12 (output) <16> Address (output) <16> <16> BA <16> <16> <16> <16> <20> <20> <18> <18> <18> <17> <17> <19> <23>
PALL
SELF <15>
<19>
xxDQM (output) L
Remark xxDQM: LLDQM, LUDQM, ULDQM, UUDQM
64
Data Sheet U13675EJ2V1DS00
PD705102
(5) Access timing of SRAM, Page-ROM and I/O
Parameter BCYST delay time (from CLKOUT) Address delay time (from CLKOUT) CSnNote delay time (from CLKOUT) R/W delay time (from CLKOUT) Data output delay time (from active, from CLKOUT) Data output delay time (from float, from CLKOUT) Data float delay time (from CLKOUT) IORD output delay time (from CLKOUT) MRD output delay time (from CLKOUT) IOWR output delay time (from CLKOUT) MWR output delay time (from CLKOUT) xxBEN delay time (from CLKOUT) Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) READY setup time (to CLKOUT) READY hold time (from CLKOUT) <27> tLZKDT <28> tHZKDT <29> tDKRD <30> tDKMRD <31> tDKWR <32> tDKMWR <33> tDKBEN <34> tSDTK <35> tHKDT <36> tSRYK <37> tHKRY 2 3 2 2 2 2 2 5 2 7 3 12.5 20 12.5 12.5 12.5 12.5 12.5 ns ns ns ns ns ns ns ns ns ns ns Symbol <15> tDKBC <16> tDKA <19> tDKCS <21> tDKRW <26> tDKDT Condition MIN. 2 2 2 2 2 MAX. 12.5 12.5 12.5 12.5 12.5 Unit ns ns ns ns ns
Note CSn indicates CS1 through CS7. Depending on the n value, a different area is used. n = 1 to 7: When SRAM (ROM) is selected n = 7: When Page-ROM is selected n = 3 to 6: When I/O is selected Remark xxBEN: LLBEN, LUBEN, ULBEN, UUBEN
Data Sheet U13675EJ2V1DS00
65
PD705102
SRAM (ROM), Page-ROM single read cycle I/O read timing
Ta CLKOUT (output) <15> BCYST (output) <16> <16> <15> <15> Ts Ts Ti
A1 to A23 (output)
<19> CSn (output) <33> xxBEN (output) <29> <33>
<19>
<29> IORD (output) <30> <30> MRD (output) <34> D0 to D31 (input) <21> R/W (output) <36> <37> READY (input) <36> <37> <21> <35>
Remarks 1. The broken lines indicate high impedance. 2. n = 1 to 7 3. xxBEN: LLBEN, LUBEN, ULBEN, UUBEN
66
Data Sheet U13675EJ2V1DS00
PD705102
SRAM (ROM) single write cycle I/O write timing
Ta CLKOUT (output) <15> BCYST (output) <16> <15>
Ts
Ts
<15>
<16>
A1 to A23 (output)
<19> CSn (output) <33> xxBEN (output) <31> IOWR (output) <32> MWR (output) <26> D0 to D31 (output) <27> D0 to D31 (output) <21> R/W (output) <36> <37> READY (input) <36> <37> <32> <31> <33>
<19>
<26>
<28>
<21>
Remarks 1. The broken lines indicate high impedance. 2. n = 1 to 7 3. xxBEN: LLBEN, LUBEN, ULBEN, UUBEN
Data Sheet U13675EJ2V1DS00
67
PD705102
Page-ROM burst read cycle (with 32-bit data bus)
Ta CLKOUT (output) <15> BCYST (output) <16> A1 to A23 (output) <19> CS7 (output)
Tb1
Tb1
Ta2
Tb2
Ta3
Tb3
Ta4
Ts
Ti
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<16>
<16>
<16>
<16>
<19>
<19>
xxBEN (output) H <30> MRD (output) <34><35> D0 to D31 (input) <21> R/W (output) <36> <37><36> <37> READY (input) <36> <37> <36> <37> <36> <37> <21> <34><35> <34><35> <34> <35> <30> <30>
Remarks 1. The broken lines indicate high impedance. 2. xxBEN: LLBEN, LUBEN, ULBEN, UUBEN
68
Data Sheet U13675EJ2V1DS00
PD705102
(6) Interrupt timing
Parameter NMI setup time (to CLKOUT) NMI hold time (from CLKOUT) INTPxx setup time (to CLKOUT) INTPxx hold time (from CLKOUT) NMI high-level time NMI low-level time Symbol <38> tSNK <39> tHKN <40> tSIK <41> tHKI <42> tNMH <43> tNML Conditions MIN. 5 7 7 3 5T + 12 5T + 12 MAX. Unit ns ns ns ns ns ns
Remarks 1. T = tCYK (external clock cycle) 2. Even if tSNK and tHKN are set to other than the above range, the NMI interrupt can be acknowledged, however, in this case NMI acknowledge timing may be delayed.
CLKOUT (output)
<38> 2.0 V NMI (input) 0.5 VDDO 0.6 V <43>
<39>
<39> <38>
<42>
<40> INTP00 to INTP03, INTP10 to INTP13 (input)
<41>
Data Sheet U13675EJ2V1DS00
69
PD705102
(7) Bus hold timing
Parameter Data active delay time (from CLKOUT) Data float delay time (from CLKOUT) HLDRQ input setup time (to CLKOUT) HLDRQ hold time (from CLKOUT) HLDAK output delay time (from CLKOUT) Address float delay time (from CLKOUT) Symbol <27> tLZKDT <28> tHZKDT <44> tSHQK <45> tHKHQ <46> tDKHA <47> tHZKA Conditions MIN. 2 3 7 3 2 3 2 12.5 20 12.5 MAX. 12.5 20 Unit ns ns ns ns ns ns ns
Address active delay time (from CLKOUT) <48> tLZKA
Ti CLKOUT (output) <44>
Tih
Th
Th
Th
Th
Ti
<44> <45>
HLDRQ (input) <46> HLDAK (output) <47> Note 1 (output) <47> Note 2 (output) <47> Note 3 (output) <47> A1 to A23 (output) <28> D0 to D31 (output) <27> <48> <48> <48> <48> <46>
Notes 1. BCYST, WE, CS0 to CS7, RAS, CAS, MRD, MWR, CKE 2. R/W, LLBEN, LUBEN, ULBEN, UUBEN 3. LLDQM, LUDQM, ULDQM, UUDQM Remark The broken lines indicate high impedance.
70
Data Sheet U13675EJ2V1DS00
PD705102
(8) DMA timing
Parameter DMARQ input setup time (to CLKOUT) DMARQ hold time (from CLKOUT) DMAAK output delay time TC output delay time Symbol <49> tSDQK <50> tHKDQ <51> tDKDAK <52> tDKTC Conditions MIN. 7 3 2 2 12.5 12.5 MAX. Unit ns ns ns ns
CLKOUT (output) <49> DMARQ0 to DMARQ3 (input) <50> <49>
<51> DMAAK0 to DMAAK3 (output)
<51>
<52> <52> TC (output)
Data Sheet U13675EJ2V1DS00
71
PD705102
(9) CSI timing (a) SCLK input mode
Parameter SCLK cycle SCLK high-level time SCLK low-level time SCLK rise time SCLK fall time SI input setup time (to SCLK) SI input hold time (from SCLK) SO output delay time (from SCLK) Symbol <53> tCYSI <54> tSIH <55> tSIL <56> tSIR <57> tSIF <58> tSDTS <59> tHSDT <60> tDSDT 21 21 2 21 Conditions MIN. 4T tCYSI/2 - 10 tCYSI/2 - 10 10 10 MAX. Unit ns ns ns ns ns ns ns ns
Remark T = tCYK (external clock cycle)
<53> <54> 0.8 VDDO SCLK (input) 0.5 VDDO 0.2 VDDO <58> SI (input) <60> <59> <55> <56> <57>
SO (output)
72
Data Sheet U13675EJ2V1DS00
PD705102
(b) SCLK output mode
Parameter SCLK cycle SCLK high-level time SCLK low-level time SCLK rise time SCLK fall time SI input setup time (to SCLK) SI input hold time (from SCLK) SO output delay time (from SCLK) Symbol <61> tCYSO <62> tSOH <63> tSOL <64> tSOR <65> tSOF <66> tSDTS <67> tHSDT <68> tDSDT 21 21 2 21 Conditions MIN. 4T tCYSO/2 - 10 tCYSO/2 - 10 10 10 MAX. Unit ns ns ns ns ns ns ns ns
Remark T = tCYK (external clock cycle)
<61> <62> SCLK (output) 0.8 VDDO 0.5 VDDO 0.2 VDDO <66> SI (input) <68> <67> <63> <64> <65>
SO (output)
Data Sheet U13675EJ2V1DS00
73
PD705102
(10) Timer timing
Parameter TI clock cycle TI clock high-level time TI clock low-level time TI clock rise time TI clock fall time TCLR clock high-level time TCLR clock low-level time Symbol <69> tCYT <70> tTIH <71> tTIL <72> tTR <73> tTF <74> tCLH <75> tCLL 4T + 10 4T + 10 Conditions MIN. 8T 4T + 10 4T + 10 10 10 MAX. Unit ns ns ns ns ns ns ns
Remark T = tCYK (external clock cycle)
<69> <70> 2.0 V TI (input) 0.5 VDDO 0.6 V <74> 2.0 V TCLR (input) 0.6 V <75> <71> <72> <73>
74
Data Sheet U13675EJ2V1DS00
PD705102
17. PACKAGE DRAWING
160 PIN PLASTIC LQFP (FINE PITCH) ( 24)
A B
120 121 81 80
detail of lead end C D S Q R
160 1
41 40
F G P
H
I
M
J K
M
N
NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.
L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 26.00.2 24.00.2 24.00.2 26.00.2 2.25 2.25 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.145+0.055 -0.045 0.10 1.40.1 0.1250.075 3 +7 -3 1.7 MAX. INCHES 1.024 +0.008 -0.009 0.9450.008 0.9450.008 1.024 +0.008 -0.009 0.089 0.089 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.0060.002 0.004 0.0550.004 0.0050.003 3 +7 -3 0.067 MAX. S160GM-50-8ED-2
Data Sheet U13675EJ2V1DS00
75
PD705102
18. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 18-1. Surface Mounting Type Soldering Conditions
PD705102GM-143-8ED: 160-pin plastic LQFP (fine pitch) (24 x 24 mm) PD705102GM-133-8ED: 160-pin plastic LQFP (fine pitch) (24 x 24 mm)
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 sec. Max. (at 210C or higher), Count: two times or less, Exposure limit: 3 daysNote (after that, prebake 125C for 10 hours) Package peak temperature: 215C, Time: 40 sec. Max. (at 200C or higher), Count: two times or less, Exposure limit: 3 daysNote (after that, prebake 125C for 10 hours) Pin temperature: 300C Max., Time: 3 sec. Max. (per pin row) Recommended Condition Symbol IR35-103-2
VPS
VP15-103-2
Partial heating
--
Note After opening dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating).
76
Data Sheet U13675EJ2V1DS00
PD705102
[MEMO]
Data Sheet U13675EJ2V1DS00
77
PD705102
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
78
Data Sheet U13675EJ2V1DS00
PD705102
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U13675EJ2V1DS00
79
PD705102
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. V830, V832, and V830 Family are trademarks of NEC Corporation. * The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98.8

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